The present invention relates to a printed wiring board and a method producing such a printed circuit.
Known printed wiring boards are produced by a method, for example, disclosed in Japanese Unexamined Patent Publication No. 2005-86164 (referred to as document 1, hereinafter).
The method disclosed in the document 1 is as follows: Prepared is a core substrate containing glass cloth. First and second wiring layers are formed on both sides of the core substrate and connected to each other through interstitial via holes (IVH). A B-staged insulative sheet containing glass cloth and copper foil are placed in this order on each wiring layer and laminated by thermal press. The laminated and cured insulative sheet is turned into an insulating layer.
The copper foil is then selectively etched to have openings for via holes. The portions of the insulating layer that correspond to the openings are removed by laser processing to have the via holes, followed by coating of a plated layer over the inner wall of each via hole and also the copper foil.
The plated layer and the copper foil are selectively removed by subtractive etching, a known technique to selectively etch a conductive layer to form a wiring layer. The etching process forms a third wiring layer on the first wiring layer connected to each other through the via holes and also a fourth wiring layer on the second wiring layer connected to each other through the via holes, thus providing a known printed wiring board.
Generally, thinner printed wiring boards suffer from lower stiffness. The known printed wiring board produced by subtractive etching, however, enjoys higher stiffness than those having insulating layers made of resin only, thanks to glass cloth contained in the core substrate and each insulating layer.
Thus, the known printed wiring board having the high-stiff glass cloth coated over the core substrate and each insulating layer is thought to be advantageous in achieving thinner structures.
Each conductive layer in the known printed wiring board is, however, relatively thick due to its dual-layer structure of the copper foil and the plated layer. It is also well known that subtractive etching causes difficulty in forming a finer wiring pattern on a thicker conductive layer.
There is thus demand for improvements in production of multilayer build-up wiring boards, such as the known one disclosed in the document 1, for finer and denser wiring patterns.
A method for achieving such finer and denser wiring patterns is disclosed in Japanese Unexamined Patent Publication No. 2000-36659 (referred to as document 2, hereinafter).
The method disclosed in the document 2 is as follows: Copper foil coated over an insulating layer and having via holes formed therethrough is completely etched away, to expose the insulating layer. A plated layer is formed on the exposed insulating layer by semi-additive processing, a known technique for forming a wiring layer by selective electroplating. The plated layer is used as the third wiring layer and also the fourth wiring layer (corresponding to those discussed above), after subjected to necessary processing steps. The third and fourth wiring layers formed in this way have a singly-layer structure because of complete etching removal of copper foil, thus becoming thinner than those formed by subtractive etching.
Consequently, the method disclosed in the document 2 is thought to achieve finer and denser wiring patterns.
The method disclosed in the document 2, however, could lower the reliability of via holes on connectability. This is because that the first and second wiring layers (corresponding to those discussed above) become thinner due to the fact that the surface portions of the wiring layer (the bottoms of via holes) are also removed when copper foil is etched away.
The method disclosed in the document 2 thus requires highly precise management to etching requirements. For example, the thickness of copper foil must be adjusted within a specific range in order that the first and second wiring layers do not give adverse effects to the reliability of via holes on connectability, after etching.
Moreover, as discussed, the method in the document 2 involves the process of removing copper foil to expose its under layer, or an insulating layer, and forming a plated layer on the exposed layer.
However, it is a well known fact that such a process cannot give sufficient adhesiveness to the interface of a plated layer and an insulating layer. “Sufficient” adhesiveness means, for example, 8 N/cm or higher in peel strength in compliance with JIS standards, JIS C 6481.
Measurements to a printed wiring board produced in the same as the one discussed above by the inventors of the present invention revealed 15 N/cm in peel strength for copper foil and an insulating layer whereas 6 N/cm in peel strength for a plated layer and the insulating layer.
Thus, it must be addressed that the method of producing a printed wiring board disclosed in the document 2 require improvements in adhesiveness between a plated layer (wiring layer) and an insulating layer.